Independent of the flash memory manufacturer, flash memories are exposed to a non-negligible raw bit error rate. Past research activities have studied and identified the reasons of these raw bit errors including program disturbance from tunneling and hot-electron injection, quantum-level noise effects, erratic tunneling, data retention due to stress-induced leakage currents (SILC) and read disturbance as well as detrapping-induced retention. Error-correcting codes (ECC) are put in place in order to achieve a better reliability. Reed Solomon (RS) or Bose-Chaudhuri-Hocquenghem (BCH) codes can be used for this purpose. Some hardware manufacturers explicitly recommend the usage of 4-bit ECC.
ECCs are characterized by the number of errors they can correct (t_c) as well as the number of errors they are capable to detect (t_d) where t_c<=t_d. If there happen to be more errors in a data block than can be detected, then there is a higher risk of miscorrection. The probability that more errors occur than can be detected can be reduced by choosing the parameters of the ECC accordingly.
An ECC decoder receives an encoded codeword and calculates therefrom a value that tells whether the encoded codeword comprises one or more errors. After this calculation, the ECC decoder may try to decode the codeword. The result of the decoding of an erratic codeword can be:                the correct codeword being decoded,        a decoding failure event called an erasure, e.g., the codeword could not be corrected, or        a miscorrection resulting in an incorrect codeword.        
An ECC for a certain application is designed to reduce the probability of miscorrections to an acceptable level. Therein it is better to detect an erasure than to make a miscorrection. In case of erasures, higher-level ECCs, like C2 codes such as RAID, can be used to detect and recover these cases.
The publication “Bit Error Rate in NAND Flash Memories”, by N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, E. Schares, F. Trivedi, E Goodness, and L. R. Nevill, in IEEE 46th Annual International Reliability Physics Symposium, Phoenix, 2008 comprises an investigation of error patterns in multi-level-cell (MLC) based flash memories. The results from the analysis of four types of MLC-based NAND Flash memory devices show three type of errors, namely write errors causing cells being programmed with higher threshold voltage than intended, retention errors due to loss of electrons on the floating gate, and read distrurb errors due to a certain voltage applied to all deselected wordlines in the block. These error types cause bit errors in the sense that the threshold voltage is being moved up or down by one level.
In the article “Apparatus for improving Data Access Reliability of Flash Memory”, by Jen-Wei Hsieh, Tei-Wei Kuo, Hsiang-Chi Hsieh, US Patent Application US2007/0266298A1, November 2007, a method is proposed that uses the exact value of the threshold voltage to indicate whether the measured voltage is in a reasonable range. If not, the cell read will be marked as suspicious. This information can then be used in ECC decoding to indicate where the error lies and hence improve data access reliability. This method is meant to be integrated on a flash chip directly, since access to the exact threshold voltage value is needed. If the measured threshold voltage exactly matches an incorrect level, then this method can't detect the error location.
U.S. Pat. No. 5,475,693 is directed to an error management process for flash EEPROM memory arrays. It describes a method of utilizing error-detecting and -correcting circuitry to detect and correct errors which can occur in data stored in multi-bit per cell format in a flash EEPROM memory array before those errors can affect the accuracy of data provided by that flash EEPROM memory array. This method comprises detecting errors present in a sector of an array being read, terminating the detection process if no errors are detected, correcting the errors if less than a first number of errors are detected, retrying the detection of errors in the sector of an array if greater than the first number of errors is detected, correcting the errors after the retrying if less than a second number of errors greater than the first number of errors are detected, marking the block of the array as questionable if more than the second number of errors but less than a third number of errors—which is the greatest the error detection process is able to correct—is detected; and then correcting the errors which are detected. The method tries to recover from more than a given number of errors by retrying, including retrying at lower read speed. If the retry fails, and the block had been marked questionable previously, it will be permanently removed from service. The method only relies on the used ECC. In a particular embodiment, the ECC detects six errors and can correct up to five errors. Consequently, a block with more than five errors is immediately marked as bad.
U.S. Pat. No. 6,209,113 is directed to a method and apparatus for performing error correction on data read from a multistage memory. According to one embodiment, a cell in a memory device is read to generate a read voltage determined by a state of the cell and one of an ordered succession of encoded signals is selected based on the read voltage, where each encoded signal corresponds to a field of bits and adjacent encoded signals correspond to respective fields of bits that are different only in a single bit. The selected encoded signal is decoded to generate a field of uncorrected bits and a field of syndrome bits indicating any error in the uncorrected bits. The syndrome bits are decoded to generate correction bits to correct the error, and the uncorrected bits are combined with the correction bits to generate a field of corrected bits. The method includes the steps of encoding data read from each memory element of the array, detecting an error in the encoded data from one memory element, and correcting the error by changing a selected number of bits of the encoded data. This method uses Gray coding so that there can be only one erroneous bit in a cell. Therefore, the decoder being used only has to correct a small number, preferably one, of bits per cell, instead of potentially all bits in the cell, which reduces the amount of ECC data to be stored. The method does error correction decoding first and then accepts the correction only if the error changes the one bit per symbol. This method does not allow to correct more errors than the ECC decoder is capable of correcting.
US2008/0168319 is directed to a flash memory device error correction code controller. An ECC controller for a flash memory device stores M-bit data, where M is a positive integer equal to or greater than 2, and includes an ECC encoder and an ECC decoder. The ECC encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The ECC decoder calculates the number of errors in the data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors. The method uses two error correction schemes. Preferably, one of the schemes is faster, but corrects less errors than the other. Depending on the number of errors detected, one of the schemes is used to correct the error. The scheme requires to store the redundant bits for both correction schemes, and hence significantly increases the amount of redundant information without being able to correct more errors.
U.S. Pat. No. 7,450,425 is directed to a method for non-volatile memory cell read failure reduction. One embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations. In various embodiments an ECC check pass can also occur when the data being read contains a number of erroneous bits which are correctable by the ECC decoder. The threshold number of bits correctable by a ECC decoder can depend on the particular ECC technique being employed. Some ECC techniques can correct single-bit errors, while others can correct double-bit errors or other higher numbers of bit errors. In instances in which the read data includes fewer than the threshold number of cells correctable by the ECC decoder, the ECC decoder can correct the erroneous bits prior to providing the read data to a controller. When reading from a flash cell, an appropriate voltage is applied to the control gate and the drain. The comparison of the drain-to-source current, which indicates the threshold voltage of the cell against a reference current, allows to determine the state of the memory cell. The method varies the reference current in case the data could not be recovered using the ECC decoder and performs subsequent read operations on the same cell. The process is repeated until the ECC decoder can in fact recover the data, or a given amount of steps have been tried without success. In the latter case a read error is returned. This method utilizes the analog the threshold voltage signal in the flash memory chip. However, a solid-state memory controller manufacturer may not have access to the threshold voltage signal. Also, the method introduces delay and complexity by applying a number of additional read operations with varied voltage steps in to any direction to a single read potential. This method also introduces the likelihood of read-induced errors.
U.S. Pat. No. 6,839,875 is directed to a method and apparatus for performing error correction on data read from a multistage memory. The method for performing error correction on data read from a multistate memory array works by encoding data read from each memory element of the array, detecting an error in the encoded data from one memory element, and correcting the error by changing X bits of the encoded data (preferably X=1), and a multistate memory system for performing the method. Preferably the system is a circuit in which each memory element is a flash memory cell. A data bit is read from each memory cell by asserting a signal having a signal value in a value range, where the value range is a member of a sequence of non-overlapping value subranges. The method also comprises encoding the voltage signal into one of a sequence of encoded signals, each of the encoded signals representing a unique ordered set of binary bits; and performing error detection and correction on the encoded signal to detect errors in the encoded signal and to correct correctable errors in the encoded signal.
US2009/0055706 is directed to a method and apparatus for flash memory error correction. In the flash memory device, a memory array comprises a main area for data storage, and a spare area for storage of parities associated with the stored data. An erasure table maintains an erasure list indicating addresses of defects in the memory array where data storage is unavailable. A processor performs error correction on the stored data based on the parities and the erasure list to output a corrected output. A flash memory device, comprises a memory array, comprising a main area for data storage, and a spare area for storage of parities associated with the stored data; an erasure table, maintaining an erasure list of defects in the memory array where data storage content maybe not correct; a processor, performing error correction on the stored data based on the parities and the erasure list to output a corrected output. An error correction method for a flash memory device, is described wherein the flash memory device comprises a memory array, comprising a main area for data storage, and a spare area for storage of parities associated with the stored data; the error correction method comprises establishing an erasure list for maintaining defects in the memory array where data storage content maybe not correct; performing error correction on the stored data based on the parities and the erasure list to output a corrected output. According to error correction theory, the ability to recover data is increased when specific addresses in the memory array are known defects. The idea is to introduce an erasure table which stores addresses of defects in order to tolerate more errors. The erasure table can be established at the manufacturing stage. New defective addresses are automatically added when detected during the error correction process. If all error locations are known, the method corrects errors up to the amount of errors detectable by the ECC decoder being used. Here, additional storage space is needed to hold the erasure table.
U.S. Pat. No. 5,864,569 is directed to a method and apparatus for performing error correction on data read from a multistate memory. This method uses the bit flipping idea in MLC Flash but requires the information being stored in a cell to be Gray encoded. Further, it is assumed that the erroneous symbol is being known.
It is therefore a challenge to provide a method for data error correction that overcomes the drawbacks of the known data error correction methods.